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| E2B0029-27-Y2 Semiconductor Semiconductor MSM6648 100-DOT COMMON DRIVER This version: Nov. 1997 MSM6648 Previous version: Mar. 1996 GENERAL DESCRIPTION The MSM6648 is a dot matrix LCD common driver. Fabricated in CMOS technology, the device consists of two 50-bit bidirectional shift registers, two 50-bit level shifters, and two 50-bit 4-level drivers. The MSM6648 is equipped with 100 LCD output pins. By connecting more than two MSM6648s in cascade, this LSI is applicable to a wide LCD panel. FEATURES * Logic supply voltage : 2.7 to 5.5 V * LCD drive voltage : 18 to 28 V * Applicable LCD duty : 1/64 to 1/240 * Suitable for bath panel sizes of 400 (200 2) and 480 (240 2) in common numbers by the use of intermediate data input and 10-bit bypass function. * Structure: Tape Carrier Package (TCP) mounting with 35 mm wide film (Product name : MSM6648AV-Z-01) Sn-plated 1/9 Semiconductor MSM6648 BLOCK DIAGRAM O1 O2 V1R V2R V5R VEER O49 O50 50-BIT 4-LEVEL DRIVER VDD VEE DF DISP OFF 50-Bit LEVEL SHIFTER VDD VSS 50-Bit BIDIRECTIONAL SHIFT REGISTER IO50 MODE2 SHL IO1 CP VDD VSS IO51 50-Bit BIDIRECTIONAL SHIFT REGISTER VDD VSS MODE1 IO100 50-Bit LEVEL SHIFTER V1L V2L V5L VEEL O51 O52 VDD 50-BIT 4-LEVEL DRIVER VEE O99 O100 2/9 Semiconductor MSM6648 PIN CONFIGURATION (TOP VIEW) O100 O99 (LCD output side) O2 O1 Surface of chip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 (Input pin side) Pin 1 2 3 4 5 6 7 8 9 10 Symbol V1L V2L V5L VEEL MODE1 IO100 DISP OFF VDD SHL IO51 Pin 11 12 13 14 15 16 17 18 19 20 Symbol IO50 VSS DF CP IO1 MODE2 VEER V5R V2R V1R 3/9 Semiconductor MSM6648 ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Voltage (1) Power Supply Voltage (2) Input Voltage Storage Temperature Symbol VDD VDD-VEE *1 VI TSTG Condition Ta = 25C Ta = 25C Ta = 25C -- Rating -0.3 to +6.5 0 to 30 -0.3 to VDD + 0.3 -30 to +85 Unit V V V C *1 V1 > V2 > V5 > VEE, VDD V1 > V2 VDD - 10V, VEE + 10V V5 > VEE V1 = V1L = V1R, V2 = V2L = V2R, V5 = V5L= V5R, VEE = VEEL= VEER RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage (1) Power Supply Voltage (2) Operating Temperature Symbol VDD VDD - VEE *1 Top Condition -- No load During LCD drive -- Range 2.7 to 5.5 14 to 28 18 to 28 -20 to +75 Unit V V V C *1 V1 > V2 > V5 > VEE, VDD V1 > V2 VDD - 7V, VEE + 7V V5 > VEE V1 = V1L = V1R, V2 = V2L = V2R, V5 = V5L= V5R, VEE = VEEL= VEER 4/9 Semiconductor MSM6648 ELECTRICAL CHARACTERISTICS DC Characteristics Parameter "H" Input Voltage "L" Input Voltage "H" Input Current "L" Input Current "H" Output Voltage "L" Output Voltage ON Resistance Supply Current Input Capacitance Symbol VIH *1 VIL *1 IIH *1 IIL *1 VOH *2 VOL *2 RON *4 ISS IEE CI Condition -- -- VI = VDD, VDD = 5.5V VI = 0V, VDD = 5.5V IO = -0.2mA, VDD = 2.7V IO = 0.2mA, VDD = 2.7V VDD - VEE = 25V, | VN - VO | = 0.25V fCP = 28kHz, VDD = 3.0V VDD - VEE = 25V, No load f = 1MHz *3 (VDD = 2.7 to 5.5V, Ta = -20 to +75C) Min. 0.8VDD VSS -- -- VDD - 0.4 -- -- -- -- -- Typ. -- -- -- -- -- -- -- -- -- 5 Max. VDD 0.2VDD 1 -1 -- 0.4 2 50 300 -- Unit V V mA mA V V kW mA pF *1 *2 *3 *4 Applicable to CP, IO1, IO50, IO100, SHL, DF, DISP OFF, MODE1, MODE2. Applicable to IO1, IO50, IO51, IO100 VN = VDD to VEE, V2 = 1/16 (VDD - VEE), V5 = 15/16 (VDD - VEE), VDD = V1, VDD = 4.5V Applicable to O1 to O100 Switching Characteristics (VDD = 2.7 to 5.5V, Ta = -20 to +75C, CL = 15pF) Parameter "H", "L" Propagation Delay Time Clock Frequency CP Pulse Width Data Setup Time Data Hold Time Rise/Fall Time of CP Symbol tPLH, tPHL fCP tWCP tSETUP tHOLD tr (CP), tf (CP) Condition -- -- -- -- -- -- Min. -- -- 63 100 100 -- Typ. -- -- -- -- -- -- Max. 3 1 -- -- -- 20 Unit ms MHz ns ns ns ns Note 1 : When display is controlled by DISPOFF pin, CP rise and fall time must be 1 ms. tWCP 0.8VDD 0.8VDD tf(CP) tr(CP) 0.8VDD 0.2VDD 0.2VDD CP tSETUP IO1 (IO50) IO51 (IO100) tHOLD 0.8VDD 0.2VDD tPLH (tPHL) 0.8VDD 0.2VDD IO50 (IO1) IO100 (IO51) 0.8VDD 0.2VDD 5/9 Semiconductor MSM6648 FUNCTIONAL DESCRIPTION Pin Functional Description * IO, IO50, IO51, IO100 These are I/O pins for the two 50-bit bidirectional shift registers. * SHL This is an input pin to select the shift direction of the two 50-bit bidirectional shift registers. Set this pin to "H" or "L" level during power-on. * MODE1, MODE2 These are input pins to select whether the two 50-bit shift registers are used as a two 50-bit application or a 40-bit and 50-bit application. Functions of the SHL, MODE1 and MODE2 pins are shown below. SHL MODE1 MODE2 Scan Data Scan Function The scan data input into the IO1, and IO51 pins are shifted at the falling edge of CP and are output from the O51 AE O100 O50 AE O1 H L -- O100 AE O51 O11 AE O50 L -- H O51 AE O100 IO51 IO100 IO100 IO1 IO51 IO50 IO51 IO50 IO100 IO1 IO50 and IO100 pins after the lapse of 50 clock pulses. The scan data input into the IO100 and IO50 pins are shifted at the falling edge of CP and are output from the IO51 and IO1 pins after 50 clock pulses. This condition means a mode of bypassing between the O1 and O10 pins. The scan data input into the IO1 pin is stored in the O11 pin and is output from the IO50 pin after 40 clock pulses. The operation in the O51 to O100 pins is the same as that in setting SHL to "L" and MODE2 to "L". This condition means a mode of bypassing O50 AE O1 H H -- O90 AE O51 IO100 IO51 IO50 IO1 between the O91 and O100 pins. The scan data input into the IO100 pin is stored in O90 and is output from the IO51 pin after 40 clock pulses. The operation in the O1 to O50 pins is the same as that in setting SHL to "H" and MODE1 to "L". direction input pin output pin O1 AE O50 IO1 IO50 L -- L 6/9 Semiconductor MSM6648 * CP This is a clock pulse input pin for two 50-bit bi-directional shift registers. Scan data is shifted at the falling edge of a clock pulse. * DF This is an input pin for an LCD drive waveform AC synchronization signal, which generally inputs a frame inversion signal. See the Truth Table. * DISP OFF This is an input pin used to control the output pins O1 to O100. Signals on the V1 level are output from the output pins O1 to O100, independent of the shift register data during low signal input. See the Truth Table. * O1 to O100 These are 4-level driver output pins, directly corresponding to each bit of the shift register. DF signals combined to shift register data select and output any of four levels V1, V2, V5, and VEE. * VDD, VSS These are power supply pins. VDD is normally 2.7 to 5.5 V. VSS is a grounding pin, which is normally set to 0 V. * V1L, V2L, V5L, VEEL, V1R, V1R, V5R, VEER These are LCD drive bias voltage pins. The V1 pin may be separated from the VDD pin. Bias supply voltages are supplied from an external source. Truth Table DF L L H H Shift register data L H L H DISP OFF H H H H L Driver output (O1 to O100) V2 VEE V5 V1 V1 : Don't care NOTES ON USE Note the following when turning power on and off: The LCD drivers of this IC requires a high voltage. If a high voltage is applied to them with the logic power supply floating, excess current flows. This may damage the IC. Be sure to carry out the following power-on and power-off sequences. When turning power on: First turn on the logic circuits, then the LCD drivers, or turn on both of them at the same time. When turning power off: First turn off the LCD drivers, then the logic circuits, or turn off both of them at the same time. 7/9 Semiconductor MSM6648 APPLICATION CIRCUITS Example of connecting to LCD panel In the case of 400 (200 2) lines DATA O1 1st line O100 DATA O100 100th line O1 O1 101st line O100 O100 200th line O1 upper screen lower screen DATA O1 1st line O100 DATA O100 100th line O1 O1 101st line O100 O100 200th line O1 8/9 Semiconductor In the case of 480 (240 2) lines MSM6648 O1 O10 DATA O11 O100 O1 10 pins not used 10 pins not used 1st line 90th line 91st line O100 O91 O90 O1 O100 DATA O100 O1 O50 DATA O51 O100 O1 190th line 191st line 240th line 1st line 50th line 51st line O1 O100 O51 O50 O1 O100 DATA upper screen lower screen O100 O1 O90 O91 O100 150th line 151st line 240th line 10 pins not used 10 pins not used O1 O100 O11 O10 O1 9/9 |
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